I know old VHDL, is there any difference between 2008 and the former standard (90 something)?
Is it as big as SystemVerilog is compared to Verilog?
I know SystemVerilog 2012/2017 well enough, par except the SVA bullshit because nothing really supports it anyway, except Cadence.
A lot of companies (i.e. Antmicro) seem to transition to Cocotb.
I know that this question may sound stupid but the support for VHDL (as much as I like it) is dwindling as SV gained traction. Iirc mostly Academia (can tell fron experience) seems to like it the most.