Zen 6 = AM5 socket, launching sometime in 2026. It will use 12-core unified CCX chiplets with 48 MiB L3 cache (from current 8-core and 32 MiB) made on TSMC N2X, for up to 24 cores. Possible additional 2 "Zen LP" cores in the I/O chiplet (TSMC N4C), technically giving you up to 26 cores, 52 threads. The I/O chiplet will be physically touching the CPU chiplets, with a silicon bridge connecting them, for lower latency than the basic chiplet design used since Zen 2. There's probably a bigger iGPU or NPU included.
Zen 3/4/5 X3D use a 64 MiB 1-layer cache chiplet, for 96 MiB total in a single CCD. Zen 6 X3D should bump that to 96 MiB for 144 MiB total. If they go 2-layer (doubt it), you'd get 240 MiB.
Zen 7 should be on the new AM6 socket, with DDR6 memory, use TSMC A14, for 16-core chiplets and up to 32 cores. So two core count increases in a row,

. The consumer desktop version is not expected to disaggregate L3 cache from the CCD so maybe they'll bump it up to 64 MiB on a CCD.