it has been partially designed to serve as an ir since a very long time ago, with special features like the #line preprocessor directive
don't forget that at least 93 scheme implementations and 2 common lisp implementations compile to c
when are we going to see a soylang that compiles to gcc ir
The GCC IR has a name and it's lovely: GIMPLE. https://gcc.gnu.org/onlinedocs/gccint/GIMPLE.html
The thing is, Stallman and co shot themselves in the foot deliberately to make it difficult/impossible to target the GCC intermediate representation to dissuade proprietary tools from using it.
why would they do this? it would only just make maintaining their own frontends way harder for no real reason
it is copyright infringement to write a proprietary compiler frontend for gcc because gcc is under the gnu gpl, they do not need to make the ir hard to target
Not if you have a standardized, or at least documented, IR you can target instead of actually involving any of the GCC code. Sun/Oracle litigated api copyrights in court and lost iirc.
x 6 x 2 x 2 x 2
One interesting compiler quirk regarding ASM is how they seem to prefer lea to add. From what I understand, due to how many CPU instruction pipelines are set up, when lea and add are converted into microcode, the delegation to the MMU from lea is faster than the corresponding ALU delegation for add.while we're on the topic of gcc i recently made a high effort shitpost using its inline assembler
it was kind of fun but the moral of this story is that i should probably stick to using glibcReactions:
makes sense because you want to be able to offset pointers really fast
when it's something like 3 cycles versus 2 cycles, that's a good 33% to shave off
i did some cursory reading and
Well, in CISC architectures, many instructions are decoded into microcode. The instruction set you see when you write x86 assembly is what's called an ISA, it's kind of analogous to an ABI/API. The CPU has fairly large internal register banks it uses while executing the pipeline or doing speculative execution, which get 'committed' to the ISA registers after the instruction is completed. It's part of why branch optimization is so useful. When the cache, branch predictor, etc. are warmed up, the cpu is often looking ahead some number of instructions and preforming prefetches, out of order execution, etc.
That's what it's historically been used for. Use of
lea means that you can get a move, an arithmetic left shift of a register by 0, 1, 2, or (with AMD64) 3 bits, a register addition, and an addition of an immediate value all rolled up into one instruction as long as you don't need the result to set condition codes and aren't using the stack pointer register as one of the operands.lea eax, [4*ebx + ecx + 42]mov eax, ebx
sal eax, 2
add eax, ecx
add eax, 42
Was there ever any doubt?
Retard it's Rust. The entire thing from top to bottom is a troon creation. No surprise there
I’ve seen lea used to implement FMA a lot, linear transforms like that are ridiculously common both in addressing and also in calculations
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I love learning about how the CPU works, so much of what we do in programming is kind of conceptual with design patterns and abstractions and the like, but at the end of the day, there's a really intensely engineered little chip that you may ignore at your own peril. Finding out how to write code that works at a high level while also functioning appropriately when the rubber hits the road is a never ending process.
