Which language did God code the universe in? - Only God can make a tree?

The Holy Language?

  • Total voters
    108
MIPS assembly, just like God's dad intended.

Pictured: a young God polishing a Halo array in his dads workshop.
games comp mips assembly Introduction-To-MIPS-Assembly-Language-Programming-OpenLibra.gif
 
  • Like
Reactions: topsikrets, glib, Anal Eclipse and 2 others
OP forgot 7_4. It's what Brad claims he coded the universe in.
 
Anal Eclipse said:
Learning MIPS in my computer architecture class was very interesting. My group even made a MIPS emulator. Also cool to know PS1 and PS2 CPU was MIPS based.
Click to expand...
MIPS is a mishmash of strange architectural decisions that don't really make sense, for example full width 32 bit instructions and delay slots. However I guess with any once popular architecture, there's still millions of devices floating around out there so it's worthwhile to be familiar with. A lot of universities start with MIPS when Z80 or MOS 6502 would be good starting points too. Both were invented almost fifty years ago and probably billions of them are still in use.
 
  • Informative
Reactions: Anal Eclipse
awoo said:
MIPS is a mishmash of strange architectural decisions that don't really make sense, for example full width 32 bit instructions and delay slots. However I guess with any once popular architecture, there's still millions of devices floating around out there so it's worthwhile to be familiar with. A lot of universities start with MIPS when Z80 or MOS 6502 would be good starting points too. Both were invented almost fifty years ago and probably billions of them are still in use.
Click to expand...
Couldn't a delay slot be used as a kind of user definable OoE in a strange way? What's up with full width 32bit instructions?
 
Smaug's Smokey Hole said:
Couldn't a delay slot be used as a kind of user definable OoE in a strange way? What's up with full width 32bit instructions?
Click to expand...
@AmpleApricots can probably elaborate on this further, but delay slots were a possible optimization I guess for loading instructions that turned out to not be useful. Since MIPS is 32 bit, instructions that are word aligned are much easier to decode ahead of time, but at the expensive of wasting a lot of bits in terms of instruction density. Well my guess is that throughput and cache sizes are so important that it's worth having more complicated instruction decoding for packing more instructions into one space. IIRC Intel Core era processors had four distinct instruction decoder units. I'm not really knowledgeable in this area but it is an interest for me.
 
  • Informative
Reactions: Smaug's Smokey Hole
awoo said:
MIPS is a mishmash of strange architectural decisions that don't really make sense, for example full width 32 bit instructions and delay slots. However I guess with any once popular architecture, there's still millions of devices floating around out there so it's worthwhile to be familiar with. A lot of universities start with MIPS when Z80 or MOS 6502 would be good starting points too. Both were invented almost fifty years ago and probably billions of them are still in use.
Click to expand...
Delay slots exist because of the instruction pipeline. MIPS was designed to run up to one instruction per cycle, but since instructions may need multiple cycles, their execution times will overlap. A jump or branch instruction won't finish by the time the next instruction has already begun to execute. This problem affects all pipelined CPUs to some degree. Intel solved this issue in their first pipelined x86 CPU (the 486) by simply waiting (stalling the pipeline) on (conditional) branch instructions, which naturally imposes a performance penalty. Modern CPUs do branch prediction (and roll back the results if they guess wrong) or speculative execution (they execute both branches and discard the results from the branch that ended up not being taken).
 
  • Like
Reactions: awoo
You must log in or register to reply here.
Back