* Zen 6 will be on AM5

%, with 12-core unified CCDs and up to 24 cores for desktop.
* Zen 6 supports 3D V-Cache directly on the CCDs (or not present) as usual.
* APUs share CCDs with desktop, and could have 3D V-Cache, but again, no indications other than it's possible.
* The Medusa Point APU is on FP10.
* Medusa Point appears to have 8 workgroups / 16 CUs again. Which is fine since the current Strix Point APU doesn't scale well from 12 to 16 CUs, bandwidth is more important. No confirmation of anything like Infinity Cache yet.
* Medusa Ridge desktop chips have a 155mm^2 I/O die. Speculates that it's getting larger graphics and/or an NPU.
* From the description: It might be called Olympic Ridge instead of Medusa Ridge.
* MLID is now going with TSMC N2 for the Zen 6 CCD, but it could be N3.
* The CCD and I/O die are right next to each other now, and there is a bridge die embedded in the base die underneath them.
UMC is making the bridge dies, with packaging done by
SPIL. This will lead to a "massive" latency reduction and is a "Zen 2 moment".
AMD was arguably phoning it in with the chiplet-based designs from Zen 2 to Zen 5, since it was very economical to share cheap, high yield chiplets between desktop and server chips. Now they are effectively fusing them together with the bridge dies, and this packaging is apparently good enough to be used in laptops.
Other sources have said that the Medusa Ridge I/O die will use TSMC N4C. Moving from
122mm^2 and 3.4 billion transistors on TSMC N6 to 155mm^2 on N4C means it's 27% larger. N6 to N4C should be about 1.62x density (I went with (1.8 / 1.18) * 1.06), so that should be a little over double the transistors or roughly 7 billion. Enjoy your desktop NPU.
One unanswered question for me is the L3 cache. It wasn't mentioned but the laptop APUs will suddenly have the same cache per core as desktop chips. Cezanne/Rembrandt/Phoenix have 16 MiB, Strix Point has split 16+8 MiB, while desktop chips had 32 MiB. But I wonder if AMD will increase the CCD L3 cache to 36 MiB to align better with the move to 12 unified cores.